The present invention relates to a semiconductor integrated circuit, and in particular to an effective technique that is used for a gate array employed for high integration and low power.
To appropriately support the production of a variety of small lots of ASIC (Application Specific Integrated Circuit) chips, elements such as transistors are manufactured in advance for use as base cells. Later, in addition to first layer lines provided for such cells, lines for a customized circuit, designed in accordance with customer specifications, are provided to produce ASICs that can perform functions required for particular applications. This production method thus provides means for flexibly coping with the needs of clients, and contributes to a reduction in the time required for the delivery of orders. In one type of ASIC, a gate array, p-type transistors and n-type transistors are arranged in separate arrays as basic cells. Then, when customized circuit lines for the transistors (basic cells) are added, a logic circuit that satisfies the needs of a customer can be provided. It should be noted that the transistors used for this purpose are MISFETs (Metal Insulator Semiconductor Field Effect Transistors).
FIG. 1 is a plan view of an example conventional gate array. An n well 2 and a p well 3 are formed on the main face of a semiconductor substrate 1. Gate lines 4 are formed across the n well 2 and the p well 3. Each of the gate lines 4 includes a gate electrode 4a, which functions as the gate of a MISFET, and a contact (connection region) 4b for the upper layer line. The contact 4b is formed on an element separation region 5, and a contact member for effecting a connection with the first layer line is deposited thereon. Doped regions 6, which are formed above the n well 2 on either side of gate electrodes 4a, are p-type regions, and function as the sources or the drains for p-type MISFETs. The doped regions 6, which are formed above the p well 3, are n-type regions and function as the sources or the drains of n-type MISFETs. A gate line 4, an impurity region 6 and a channel region below a gate electrode 4a constitute one MISFET.
Multiple p-type MISFETs and multiple n-type MISFETs are arranged in like arrays along the respective well regions (the n well 2 and the p well 3) in the x direction (first direction) in which the well regions are formed and extended. Adjacent MISFETs (p-type MISFETs or n-type MISFETs) share the impurity regions 6 that serve as the sources or drains. The arrays of p-type MISFETs and n-type MISFETs are located adjacent to each other in the y direction (second direction), and since the p-type and the n-type MISFETs are arranged adjacently, wiring of a CMOS circuit is facilitated.
To use this gate array to constitute an inverter, for example, only the following connections need be made. FIG. 2A is a plan view of an example inverter using the conventional gate array, and FIG. 2B is a circuit diagram for the inverter.
In FIGS. 2A and 2B, a MISFET (Qp1) that includes a gate line 4-1p and a MISFET (Qn1) that includes a gate line 4-1n are employed. In the following explanation, a p-type MISFET that includes a gate line 4-kp is denoted by Qpk (k is a natural number), and an n-type MISFET that includes a gate line 4-kn is denoted by Qnk. One of the impurity regions 6 (to the left of the gate line 4-1p) of the Qp1 and a line LVdd are connected by a contact 7, and one of the impurity regions 6 (to the left of the gate line 4-1n) of the Qn1 and a line LVss are connected by a contact 7. The other impurity region 6 (to the right of the gate line 4-1p) of the Qp1 and the other impurity region 6 (to the right of the gate line 4-1n) of the Qn1 are connected via a line L1 and contacts 7. The gate line 4-1p of the Qp1 and the gate line 4-1n of the Qn1 are connected via contacts 7 and a line L2 formed on respective contacts 4b. The line L2 corresponds to the input IN of the inverter, and the line L1 corresponds to the output OUT of the inverter.
Further, to use the gate array to constitute a NAND circuit, for example, only the following connections need be made. FIG. 3A is a plan view of an example NAND circuit using the conventional gate array, and FIG. 3B is a circuit diagram showing the NAND circuit. It should be noted that the well regions are not shown in the plan views following FIG. 3 for the simplification of the drawings.
The NAND circuit comprises an MISFET (Qp2) that includes a gate line 4-2p, an MISFET (Qp3) that includes a gate line 4-3p, an MISFET (Qn2) that includes a gate line 4-2n, and an MISFET (Qn3) that includes a gate line 4-3n. One impurity region 6 of the Qp2 and one impurity region 6 of the Qp3 are connected to a line LVdd via contacts 7 and one impurity region 6 of the Qn3 is connected to a line LVss via a contact 7. The impurity region 6 shared by the Qp2 and the Qp3 and the impurity region 6 of the Qn2 are connected via a line L3 and contacts 7. The gate line 4-2p of the Qp2 and the gate line 4-2n of the Qn2 are connected via a line L4 in the same manner as described above, and the gate line 4-3p of the Qp3 and the gate line 4-3n of the Qn3 are connected via a line L5. The line L5 corresponds to the input IN2 of the NAND circuit, the line L4 corresponds to the input IN3 of the NAND circuit, and the line L3 corresponds to the output OUT of the NAND circuit.
The first layer lines (LVdd, LVss and L1 to L5) are formed on an interlayer insulating film (not shown) that covers the gate lines, and generally are composed of a metal such as tungsten, or of polysilicon. The contacts 7 are conductive members provided inside connection holes that are formed in the interlayer insulating film. The contacts 7 are made of the same material as the first layer lines, or are separately provided as a plug from the first layer line.
When arbitrary lines are employed for the gate array as has previously been described, logic circuits can be produced. For an inverter or a NAND circuit, the gate lines of p-type MISFETs and n-type MISFETs can be interconnected by using the shortest possible lines (L2, L4 and L5) to connect adjacent, vertically arranged (in the y direction) MISFETs.
However, for a latch circuit in FIGS. 4A and 4B, the gate lines of a diagonally arranged p-type and n-type MISFET must be connected. FIG. 4A is a plan view of a latch circuit using the conventional gate array, and FIG. 4B is a circuit diagram of the latch circuit.
When two MISFETs having the input IN4 terminal of the latch circuit as a gate input terminal are defined as Qp4 and Qn4, the gate line 4-4p of the Qp4 and the gate line 4-4n of the Qn4 are connected by the shortest line (line L6), as is shown in FIG. 4B. Since it is rational that MISFETs adjacent to Qp4 and Qn4 should be selected as those connected in series to Qp4 and Qn4, Qp5 and Qn5 are selected.
However, the gate line 4-5p of Qp5 should not be connected to the gate line of Qn5, but must be connected to the gate line of another n-type MISFET (Qn7 in FIG. 4A). Further, the gate line 4-5n of Qn5 must be connected to the gate line of a p-type MISFET (Qp6 in FIG. 4A) other than Qp5. Therefore, as is shown in FIG. 5, when the gate line 4-5n and the gate line 4-6p are connected by using the line L7 which travels the shortest distance, the gate lines 4-5p and 4-7n have to be connected by detouring around line L8. It should be noted that FIG. 5 is a plan view of a portion extracted from FIG. 4A.
When the lines intersect for the interconnection of the gate lines of a p-type MISFET and an n-type MISFET, as described above, a line for detouring around a line (first layer line) for connecting gate lines must be found, so that devices located in dotted regions (4-6n and 4-7p) in FIG. 5 can not be employed. Further, since the area occupied by the first layer line is increased, there are devices that can not be employed due to the line layout.
Whereas, an increased demand has arisen for reductions in the costs of ASICs, a reduction in chip size is required in order to eliminate as many useless devices as possible. This is especially true since many latch circuits are employed for a chip, and useless devices should be eliminated as soon as possible.
It is, therefore, one object of the present invention to provide a layout for facilitating the interconnection of gate lines of devices (MISFETs) in gate arrays that are diagonally positioned.
It is another object of the present invention to increase gate array wiring efficiency and to reduce the number of devices required to implement the same function, so that reductions in manufacturing costs can be accelerated.
An overview of the present invention will now be given. One part (a connection region) of the gate lines of adjacent MISFETs is extended and formed between a p-type MISFET and an n-type MISFET that constitute a gate array. That is, the connection regions are so formed that vertically (in the y direction: second direction) the connection region (extended contact region) of an n-type MISFET, the connection region of an adjacent MISFET and the connection region of a p-type MISFET appear in the named order (and all have the same location along the first direction). In other words, at least some of the gates of a set of p-type transistors (or of a set of n-type transistors) constitute an extended-contact subset of the set of contacts and extend along the first direction such that they overlap an adjacent transistor gate (of the same set, - or p-) along the first direction; i.e. one of the extended contacts is located at the same location along the first direction as an adjacent contact.
Specifically, the present invention has the following configuration. A semiconductor integrated circuit according to the present invention comprises: a semiconductor substrate (1); an n-type region (2) on the semiconductor substrate; a p-type region (3) on the semiconductor substrate; an element separation region (5) between the n-type region and the p-type region; p-type transistors (transistors including 4-20 and 21p, Qp30 to Qp37 and Qp40 to Qp47) that are arranged on the n-type region adjacently in a first direction (x); n-type transistors (transistors including 4-20 and 21n, Qn30 to Qn37 and Qn40 to Qn47) that are adjacently arranged on the p-type region in the first direction (x); and a connection region (10) that is formed on the element separation region (5) and that constitutes one part of control lines (4-20p, 4-21p, 4-20n, 4-21n, 4-30p to 37p, 4-30n to 37n, 4-40p to 47p and 4-40n to 47n) of the p-type or the n-type transistors, wherein the connection region (10) includes a portion that is extended between second transistors (transistors including 4-20p, Qq32 and Qp42), which are arranged in the first direction (x) adjacent to first transistors (transistors including 4-21p, Qp33 and Qp43) that include the connection region (10) as one part of the control lines, and third transistors (transistors that include 4-20n, Qn32 and Qn42), which are arranged adjacent to the second transistors in a second direction (y) perpendicular to the first direction.
For convenience, the following description of the symbols is collected in one place.
For the semiconductor integrated circuit, control lines (4-21p, 4-33p and 4-43p) of the first transistors are connected to control lines (4-20n, 4-32n and 4-42n) of the third transistors by using first lines (L9 and L12), and control lines (4-20p, 4-32p and 4-42p) of the second transistors are connected to control lines (4-21n, 4-33n and 4-43n) of fourth transistors (transistors including 4-21n, Qn33 and Qn43), which are arranged adjacent to the first transistors in the second direction (y) and adjacent to the third transistors in the first direction (x), by using second lines (L10 and L13) that differ from the first lines.
The transistors constitute a gate array. A gate region (4a) on the transistors has a space wherein three lines (L9 to L18) that extend in the first direction (x) can be laid in the second direction (y).
When the connection region is thus formed, the degree of freedom for the design of the first layer lines connected to the gate lines can be increased, and diagonally located devices can be easily connected. Further, since first layer lines need not be detoured, the occurrence of useless devices can be limited, and area occupied by the arranged lines can be reduced.